Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual page 31

8. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter E18 for the
P Package Pin (the FPGA pins to which the system clock is connected), and make sure
the Frequency (MHz) is set to 300
X-Ref Target - Figure 2-7
KCU1250 IBERT Getting Started Guide
UG1061 (v2017.4) December 20, 2017
(Figure 2-7). Click OK.
Figure 2-7: Customize IP - Clock Settings
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Chapter 2: Creating the GTH IBERT Core
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