Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual page 27

Characterization kit ibert, vivado design suite
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4. Back on the Manage IP window, select Verilog for Target language, Vivado Simulator
for Target simulator, Mixed for Simulator language, and a directory to save the
customized IP
Make sure the directory name does not include spaces.
Note:
X-Ref Target - Figure 2-3
KCU1250 IBERT Getting Started Guide
UG1061 (v2017.4) December 20, 2017
(Figure
2-3). Click Finish.
Figure 2-3: Manage IP Settings
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Chapter 2: Creating the GTH IBERT Core
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