Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual page 8

All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad that interfaces with Samtec Bulls Eye connectors.
pad. Figure 1-2
X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the GTH reference clocks in the
IBERT demonstrations.
connectors on the clock module which can be connected to the reference clock cables.
X-Ref Target - Figure 1-3
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
Note:
SuperClock-2 module.
KCU1250 IBERT Getting Started Guide
UG1061 (v2017.4) December 20, 2017
B shows the connector pinout.
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
Figure 1-3 shows the locations of the differential clock SMA
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
www.xilinx.com
Chapter 1: KCU1250 IBERT Getting Started Guide
Figure 1-2 A shows the connector
GTH
Connector
Pinout
8
Send Feedback