Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual page 12

Starting the SuperClock-2 Module
The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. Configure the SuperClock-2 module using the Xilinx XC7Z010CLG225 Zynq-7000
AP SoC System Controller command line, which can be accessed through a serial
communication terminal connection using the enhanced communication port of the
Silicon Labs USB to Dual UART Bridge
Silicon Labs USB-to-UART is available in Silicon Labs CP210x USB-to-UART Installation
Guide (UG1033)
Review the KCU1250 Board User Guide (UG1057)
the System Controller.
X-Ref Target - Figure 1-9
2. Set the System Controller configuration DIP switches (SW13) to the OFF position
(Figure 1-10). This disables configuration of the FPGA at power reset.
X-Ref Target - Figure 1-10
KCU1250 IBERT Getting Started Guide
UG1061 (v2017.4) December 20, 2017
(Figure
[Ref 3].
Figure 1-9: Silicon Labs Enhanced COM PORT
Figure 1-10: Configuration DIP Switch (SW13)
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Chapter 1: KCU1250 IBERT Getting Started Guide
1-9). Additional information about the
[Ref 1] for additional information about
ON
ENABLE
ADDR0
ADDR1
ADDR2
ADDR3
12
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