Load And Store With Byte-Reverse Instructions - Xilinx Virtex-II Pro PPC405 User Manual

Integer Load and Store Instructions
Table 3-19: Store Halfword Instructions
Mnemonic
sth Store Halfword
sthu Store Halfword with Update
sthx Store Halfword Indexed
sthux Store Halfword with Update Indexed
Store Word
Table 3-20
contents of rS into the specified word location in memory.
Table 3-20: Store Word Instructions
Mnemonic
stw Store Word
stwu Store Word with Update
stwx Store Word Indexed
stwux Store Word with Update Indexed

Load and Store with Byte-Reverse Instructions

Table 3-21
(using big-endian memory) how bytes are moved between memory and the GPRs for each
of the byte-reverse instructions. When an lhbrx instruction is executed, the unloaded bytes
in rD are cleared to 0.
When used in a system operating with the default big-endian byte order, these instructions
have the effect of loading and storing data in little-endian order. Likewise, when used in a
system operating with little-endian byte order, these instructions have the effect of loading
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Name
Register-indirect with immediate index
EA = (rA|0) + d
Register-indirect with immediate index
EA = (rA) + d
rA ← EA
rA ≠ 0
Register-indirect with index
EA = (rA|0) + (rB)
Register-indirect with index
EA = (rA) + (rB)
rA ← EA
rA ≠ 0
lists the PowerPC store word instructions. These instructions store the entire
Name
Register-indirect with immediate index
EA = (rA|0) + d
Register-indirect with immediate index
EA = (rA) + d
rA ← EA
rA ≠ 0
Register-indirect with index
EA = (rA|0) + (rB)
Register-indirect with index
EA = (rA) + (rB)
rA ← EA
rA ≠ 0
lists the PowerPC load and store with byte-reverse instructions.
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Addressing Mode
Addressing Mode
R
Operand
Syntax
rS,d(rA)
rS,rA,rB
Operand
Syntax
rS,d(rA)
rS,rA,rB
Figure 3-20 shows
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