Xilinx Virtex-II Pro PPC405 User Manual page 369

Alphabetical Instruction Listing
mfcr
Move from Condition Register
mfcr rD
X Instruction Form
31
0 6
Description
The contents of the CR are loaded into register rD.
Pseudocode
Registers Altered
•
Exceptions
•
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
rD 0 0 0 0
1
1
rD ) ← (CR)
(
rD.
None.
Reserved bits containing a non-zero value.
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0 0 0 0 0 0
2
1
R
19 0
3
1
677