Tlb-Management Instructions; Trap Instructions - Xilinx Virtex-II Pro PPC405 User Manual

R
The effect of a subtract-immediate instruction can be achieved by using an add-immediate
instruction with a negative immediate operand. In the following table, value represents a
signed immediate operand.
Table C-17: Simplified Mnemonics for Subtract Instructions
Operation
Subtract (rA − rB)
Subtract Carrying (rA − rB)
Subtract Immediate (rA − value)
Subtract Immediate Shifted (rA − value
Subtract Immediate Carrying (rA − value)
Subtract Immediate Carrying and Record (rA − value)

TLB-Management Instructions

The simplified mnemonics for TLB-management instructions are listed in
Table C-18: Simplified Mnemonics for TLB-Management Instructions
Operation
Read TLBHI Portion of TLB Entry
Read TLBLO Portion of TLB Entry
Write TLBHI Portion of TLB Entry
Write TLBLO Portion of TLB Entry

Trap Instructions

System-trap instructions use the TO opcode field to specify the trap condition. Simplified
trap mnemonics are provided for the most common encodings of TO. These mnemonics
encode the trap condition as part of the mnemonic rather than as a numeric operand.
Table C-19
the simplified trap mnemonics. In this table, the column headed "<U" indicates an
unsigned less-than comparison and the column headed ">U" indicates an unsigned
greater-than comparison
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shows the abbreviations for the comparison operations used in the formation of
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Appendix C: Simplified Mnemonics
Simplified Mnemonic
sub rD, rA, rB
sub. rD, rA, rB
subo rD, rA, rB
subo. rD, rA, rB
subc rD, rA, rB
subc. rD, rA, rB
subco rD, rA, rB
subco. rD, rA, rB
subi rD, rA, value
subis rD, rA, value
subic rD, rA, value
subic. rD, rA, value
Simplified Mnemonic
tlbrehi rD, rA
tlbrelo rD, rA
tlbwehi rD, rA
tlbwelo rD, rA
Virtex-II Pro™ Platform FPGA Documentation
Equivalent Mnemonic
subf rD, rB, rA
subf. rD, rB, rA
subfo rD, rB, rA
subfo. rD, rB, rA
subfc rD, rB, rA
subfc. rD, rB, rA
subfco rD, rB, rA
subfco. rD, rB, rA
addi rD, rA, −value
addis rD, rA, −value
addic rD, rA, −value
addic. rD, rA, −value
Table C-18.
Equivalent Mnemonic
tlbre rD, rA, 0
tlbre rD, rA, 1
tlbwe rD, rA, 0
tlbwe rD, rA, 1
March 2002 Release