External Interrupt (0X0500) - Xilinx Virtex-II Pro PPC405 User Manual

Interrupt Reference

External Interrupt (0x0500)

Interrupt Classification
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•
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Description
An external exception is caused by an external device (usually the external-interrupt
controller) asserting the noncritical-interrupt input signal to the processor.
This exception is persistent. To prevent repeated interrupts from occurring, the interrupt
handler must clear the exception status in the appropriate device control register (DCR)
associated with the external-interrupt controller before returning.
This interrupt is enabled using the external-interrupt enable bit (EE) in the MSR. When
MSR[EE]=1, the processor recognizes exceptions caused by asserting the noncritical-
interrupt input signal and forces an external interrupt to occur. When MSR[EE]=0, the
processor does not recognize the noncritical-interrupt input signal and external interrupts
cannot occur.
External interrupts are disabled when an external interrupt occurs. The external interrupt
handler should not re-enable MSR[EE] until it has cleared the exception and saved SRR0
and SRR1. Saving these registers avoids potential corruption of the interrupt handler
should an external interrupt, programmable-interval timer interrupt, or fixed-interval
timer interrupt occur.
Affected Registers
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Noncritical—return using the rfi instruction.
Asynchronous.
Precise.
Register
SRR0 Loaded with the effective address of the next-sequential instruction to be
executed at the point the interrupt occurs.
SRR1 Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2 Not used.
SRR3
ESR
DEAR
[AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR] ← 0.
MSR
[CE, ME, DE] ← Unchanged.
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Value After Interrupt
R
509