Xilinx Virtex-II Pro PPC405 User Manual page 551

Registers
Table F-3: New Registers in the PowerPC Book-E Architecture
Notes:
1.
Machine-State Register
The PowerPC Book-E architecture redefines some of the bits in the machine-state register
(MSR).
PowerPC Book-E processors.
Table F-4: Comparison of MSR Bit Definitions
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Name
MMUCR Memory-management unit control register
PIR Processor ID Register
CSRR0 Critical save/restore register 0
CSRR1 Critical save/restore register 1
IVOR0– Interrupt-vector offset registers
IVOR15
IVPR Interrupt-vector prefix register
DEC Decrementer
DECAR Decrementer Auto Reload
1
DNVn Data-cache normal victim register
1
DTVn Data-cache transient victim register
1
DVLIM Data-cache victim limit
1
INVn Instruction-cache normal victim register
1
ITVn Instruction-cache transient victim register
1
IVLIM Instruction-cache victim limit
DBCR2 Debug-control register 2
1
DCDBTRH Data-cache debug tag registers
1
DCDBTRL
1
ICDBTRH Instruction-cache debug tag registers
1
ICDBTRL
Implemented in the 440 processor, but not defined by the PowerPC Book-E architecture.
Table F-4 compares the MSR bit definitions used by PowerPC 40x processors and
MSR Bit PowerPC 40x Family
0:5 Reserved
6 AP—Auxiliary Processor Available
7:11 Reserved
12 APE—APU Exception Enable
13 WE—Wait State Enable
14 CE—Critical Interrupt Enable
15 Reserved
16 EE—External Interrupt Enable
17 PR—Privilege Level
18 FP—Floating-Point Available
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Description
Implementation dependent
Reserved
Reserved: ILE—Interrupt Little Endian
Purpose
Memory management
Multiprocessing
Exception and interrupt processing
Timer resources
Cache control
Debugging
PowerPC Book-E Architecture
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