Timer Resources - Xilinx Virtex-II Pro PPC405 User Manual

Timer Resources

•
•
•
•
•
Table E-6: Summary of Exception and Interrupt Vector Differences
Timer Resources
The PowerPC 40x family implements new timer features. These are:
•
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Differences in exception-related bits in the machine-state register (MSR). See
Table E-3, page 851 for a summary.
A new interrupt-return instruction (rfci) that supports critical interrupts. The
PowerPC 40x family uses the rfi instruction to return from noncritical interrupts,
which is used to return from all interrupts in the PowerPC 6xx/7xx family.
New special-purpose registers for recording exception information. The PowerPC 40x
family defines two registers:
- The exception-syndrome register (ESR) used to identify the cause of an exception.
- The data exception-address register (DEAR) used to record the memory-operand
effective address of a data-access instruction that causes certain exceptions. The
data-address register (DAR) performs a similar function in PowerPC 6xx/7xx
processors.
Greater flexibility in relocating the interrupt-handler table. The exception-vector
prefix register (EVPR) supports relocating the interrupt-handler table anywhere in
physical-address space, with a base address that falls on a 64KB-aligned boundary.
The PowerPC 6xx/7xx family supports two locations for the interrupt-handler table:
0x000n_nnnn or 0xFFFn_nnnn, selected by using the MSR[IP] bit.
New exceptions and interrupts are defined. Some exceptions and interrupts
supported by the PowerPC 6xx/7xx family are not supported by PowerPC 40x
processors. Table E-6 summarizes the differences between the exception and interrupt
vectors defined by the two families. Gray-shaded cells represent unsupported
interrupt vectors. Not all processors within a family support all of the exceptions and
interrupts defined by the family.
Vector Offset PowerPC 40x Family
0x0100 Critical-Input
0x0900
0x0D00
0x0F00
0x0F20 APU Unavailable
0x1000 Programmable-Interval Timer
0x1010 Fixed-Interval Timer
0x1020 Watchdog Timer
0x1100 Data-TLB Miss
0x1200 Instruction-TLB Miss
0x1300
0x1400
0x1700
0x2000 Debug
The programmable-interval timer (PIT) register. This register decrements at the same
clock rate as the time base. Its function replaces that of the decrementer in the
PowerPC 6xx/7xx family.
www.xilinx.com
1-800-255-7778
PowerPC 6xx/7xx Family
System Reset
Decrementer
Trace
Performance Monitor
Instruction-Translation Miss
Data-Translation Miss (loads)
Data-Translation Miss (stores)
Instruction-Address Breakpoint
System Management
Thermal Management
R
855