Xilinx Virtex-II Pro PPC405 User Manual page 275

Alphabetical Instruction Listing
andi.
AND Immediate
andi. rA, rS , UIMM
D Instruction Form
28
0 6
Description
The UIMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of
register rS are ANDed with the extended UIMM field and the result is loaded into register
rA.
andi. is one of three instructions that implicitly update CR[CR0] without having an Rc
field. The other instructions are addic. and andis..
The andi. instruction can be used to test whether any of the 16 least-significant bits in a
GPR are 1-bits.
Pseudocode
Registers Altered
•
•
Exceptions
•
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
rS rA
1
1
rA ) ← (rS) ∧ ( ||
16
( 0 UIMM)
rA.
CR[CR0] .
LT, GT, EQ, SO
None.
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UIMM
1
6
R
3
1
583