Data Address-Compare Debug Event - Xilinx Virtex-II Pro PPC405 User Manual

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Data Address-Compare Debug Event

March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
If DBCR0[IA12X]=1, instruction addresses from 0 to (IAC1)-1 and (IAC2)
to 0xFFFF_FFFF fall within the range. Addresses from (IAC1) to (IAC2)-1
fall outside the range.
If DBCR0[IA34X]=1, instruction addresses from 0 to (IAC3)-1 and (IAC4)
to 0xFFFF_FFFF fall within the range. Addresses from (IAC3) to (IAC4)-1
fall outside the range.
Figure 9-7 illustrates how ranges are specified using DBCR0[IA12X]. No
shading indicates addresses that are in range and gray-shading indicates
addresses that are out of range.
(IAC1)-1 (IAC1)
Inclusive Range, DBCR0[IA12X]=0
(IAC1)-1 (IAC1)
Exclusive Range, DBCR0[IA12X]=1
Figure 9-7: IAC Address-Range Specification
Range Toggling
Range comparisons can be set to toggle between inclusive and exclusive each
time a debug event occurs on the specified range. DBCR0[IA12T]=1 enables
toggling of the DBCR0[IA12X] bit and DBCR0[IA34T]=1 enables toggling of
the DBCR0[IA34X] bit. Clearing a toggle bit disables toggling of the
corresponding range bit.
As an example, assume IA12 exclusive-range toggling is enabled (IA12T=1
and IA12X=1):
• The first IAC event occurs when an instruction address is in the exclusive
IA12 range. The processor clears IA12X to 0.
• The second IAC event occurs when an instruction address is in the
inclusive IA12 range. The processor sets IA12X to 0.
• The third IAC event occurs when an instruction address is in the
exclusive IA12 range. The processor clears IA12X to 0.
• And so on.
The IAC debug event does not set a DBSR status bit when toggling is used if
all of the following are true:
• Internal-debug mode is enabled.
• Debug exceptions are disabled.
• External-debug mode is disabled.
When toggling is enabled IAC events occur frequently. This condition
prevents the DBSR from recording their obvious occurrence when exceptions
are disabled.
A data address-compare (DAC) debug event occurs before executing a data-
access instruction. The effective address of the operand must match the value
contained in one of the two DACn registers. Aligned memory accesses
generate a single effective address that is used in checking for a DAC event.
Unaligned memory accesses, load/store multiple instructions, and load/store
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(IAC2)-1 (IAC2)
(IAC2)-1 (IAC2)
R
0xFFFF_FFFF
0xFFFF_FFFF
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