Xilinx Virtex-II Pro PPC405 User Manual page 3

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About This Book
This document is intended to serve as a stand-alone reference for application and system
programmers of the PowerPC
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Document Organization
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March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
PowerPC 405 Embedded Processor Core User's Manual published by IBM Corporation
(IBM order number SA14-2339-01).
The IBM PowerPC Embedded Environment Architectural Specifications for IBM PowerPC
Embedded Controllers, published by IBM Corporation.
PowerPC Microprocessor Family: The Programming Environments published by IBM
Corporation (IBM order number G522-0290-01).
IBM PowerPC Embedded Processors Application Note: PowerPC 400 Series Caches:
Programming and Coherency Issues.
IBM PowerPC Embedded Processors Application Note: PowerPC 40x Watch Dog Timer.
IBM PowerPC Embedded Processors Application Note: Programming Model Differences
of the IBM PowerPC 400 Family and 600/700 Family Processors.
Chapter 1, Introduction to the
PPC405 as an implementation of the PowerPC embedded-environment architecture.
This chapter also contains an overview of the features supported by the PPC405.
Chapter 2, Operational Concepts, introduces the processor operating modes,
execution model, synchronization, operand conventions, and instruction conventions.
Chapter 3, User Programming
available to application software.
Chapter 4, PPC405 Privileged-Mode Programming
and instructions available to system software.
Chapter 5, Memory-System
system, including caches. Real-mode storage control is also described in this chapter.
Chapter 6, Virtual-Memory
translation as supported by the PPC405. Virtual-mode storage control is also
described in this chapter.
Chapter 7, Exceptions and
the PPC405 and how software can use the interrupt mechanism to handle exceptions.
Chapter 8, Timer Resources, describes the timer registers and timer-interrupt controls
available in the PPC405.
Chapter 9, Debugging, describes the debug resources available to software and
hardware debuggers.
Chapter 10, Reset and Initialization, describes the state of the PPC405 following reset
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405D5 processor. It combines information from the
PPC405, provides a general understanding of the
Model, describes the registers and instructions
Management, describes the operation of the memory
Management, describes virtual-to-physical address
Interrupts, provides details of all exceptions recognized by
Preface
Model, introduces the registers
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