Xilinx Virtex-II Pro PPC405 User Manual page 242

R
DAC Exact-Address Match
Table 9-6: DAC Exact-Address Match Resources
Event Enable Bit
(DBCR1)
D1R
D1W
D2R
D2W
550
string instructions can generate multiple effective addresses, all of which are
used to check for a DAC event. The DAC event is controlled by conditions
specified in the DBCR1 register.
A variety of DAC conditions can be specified:
• Check for an exact data-address match.
• Check for a data-address match using halfword, word, or cacheline
granularity.
• Check for a data-address match within a range of addresses.
• Check for a data-address match outside a range of addresses.
Each of the above DAC conditions can be further controlled to cause a debug
event only if the matching data access is a read or a write.
If debug interrupts are enabled, the SRR2 register is loaded with the effective
address of the instruction that caused the DAC event.
A DAC exact-address match causes a debug event when the effective address
contained in the specified DACn register matches the effective address of the
operand. Read and write accesses can be checked independently. If a match
occurs, the corresponding status bit in DBSR is set to 1.
Table 9-6 shows the control bits used to enable the DAC exact-address-match
debug events, the type of access that is checked by each event, the DACn
register used in the comparison, and the debug-status register bit set when the
event occurs. Any number of DAC exact-address-match conditions can be
enabled simultaneously. DAC address-range comparison must be disabled
(DBCR1[DA12]=0).
Type of Access
DAC Register Used
Checked
Load (Read)
Store (Write)
Load (Read)
Store (Write)
The processor does not clear the DBSR status bits when DAC events fail to
occur. After a DAC event is recorded by a debugger, the corresponding status
bits should be cleared to prevent ambiguity when recording future debug
events.
Specifying Exact-Match Granularity
Software can specify an operand-size granularity for use when performing the
address comparison with each DAC register. Normally, the comparison checks
for an exact address match or a byte-granular match. The comparison can be
modified to check for halfword, word, and cache-line granular matches. This
is useful when a debugger wants to cause a DAC event to occur when any byte
in a word is accessed.
Granularity is specified using the DBCR1[D1S] size field for comparisons
against the DAC1 register and the DBCR1[D2S] size field for comparisons
against the DAC2 register. This field specifies which low-order address bits
are ignored during the comparison. Because low-order address bits are
ignored, the comparison is aligned on an address boundary equivalent to the
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Event Status Bit
(DBSR)
DAC1 DR1
DW1
DAC2 DR2
DW2
Virtex-II Pro™ Platform FPGA Documentation
March 2002 Release