Core-Configuration Register - Xilinx Virtex-II Pro PPC405 User Manual

Cache Control
Table 5-5: Data-Cache Control Instructions (Continued)
Mnemonic
Data Cache Block Clear to Zero
dcbz
dccci Data Cache Congruence Class
Invalidate
Data Cache Read
dcread
The dcbt and dcbtst instructions are implemented identically on the PPC405. On some
processor implementations, these instructions can cause separate bus operations to occur
that differentiate data-cache touches for loads from data-cache touches for stores.
dcbz establishes a cacheline without accessing system memory. It is possible for software
to erroneously use this instruction to establish a cacheline for unimplemented memory
locations. A subsequent access that attempts to update unimplemented system memory
(such as a cacheline replacement) can cause unpredictable results or system failure.

Core-Configuration Register

The core-configuration register (CCR0) is a 32-bit register used to configure memory-
system features, including:
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Figure 5-13
Table
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Name
An effective address (EA) is calculated using
register-indirect with index addressing:
EA = (rA|0) + (rB)
If the byte referenced by EA is not cached, a
cacheline is allocated for that address. The
cacheline containing the byte referenced by EA is
cleared to 0 and marked modified (dirty).
If the EA is non-cacheable or write-through, an
alignment exception occurs. The alignment-
interrupt handler can emulate the operation by
clearing the corresponding bytes in system
memory to 0.
Invalidates both data-cache ways in the
congruence class specified by the effective address
(EA). Any modified data is lost.
EA is calculated using register-indirect with index
addressing:
EA = (rA|0) + (rB)
If the byte specified by the effective address (EA) is
cached by the data cache, rD is loaded with
information from one of the two ways indexed by
the EA. CCR0 fields specify the cache way and
whether the data tag or data word is loaded into
rD. See
information.
EA is calculated using register-indirect with index
addressing:
EA = (rA|0) + (rB)
Whether cache misses cause cacheline allocation.
Whether instruction prefetching is permitted.
The size of non-cacheable requests over the processor local bus.
The priority given by the processor when it makes a request over the processor local
bus on behalf of a cache unit.
Enablement of the U0 storage-attribute exception.
Cache-debug features.
shows the format of the CCR0. The fields in CCR0 are defined as shown in
5-6.
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Operation
dcread Instruction, page 469
Operand
Syntax
rA,rB
rA,rB
rD,rA,rB
for more
R
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