Process-Id Register; Page-Translation Table - Xilinx Virtex-II Pro PPC405 User Manual

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Process-ID Register

The process-ID register (PID) is a 32-bit register used in virtual-address translation.
Figure 6-3
in
0
Table 6-1: Process-ID Register (PID) Field Definitions
Bit Name
0:23 Reserved
24:31 PID Process Identifier
The PID is a privileged SPR with an address of 945 (0x3B1) and is read and written using
the mfspr and mtspr instructions.

Page-Translation Table

The page-translation table is a software-defined and software-managed data structure
containing page translations. The requirement for software-managed page translation
represents an architectural trade-off targeted at embedded-system applications.
Embedded systems tend to have a tightly controlled operating environment and a well-
defined set of application software. That environment enables virtual-memory
management to be optimized for each embedded system in the following ways:
•
•
•
The unified 64-entry TLB, managed by software, caches a subset of instruction and data
page-translation entries accessible by the MMU. Software uses the unified TLB to cache a
subset of instruction and data page-translation entries for use by the MMU. Software is
474
shows the format of the PID register. The fields in the PID are defined as shown
Table 6-1.
Figure 6-3: Process-ID Register (PID)
Function
The page-translation table can be organized to maximize page-table search performance
(also called table walking) so that a given page-translation entry is located quickly.
Most general-purpose processors implement either an indexed page table (simple
search method, large page-table size) or a hashed page table (complex search method,
small page-table size). With software table walking, any hybrid organization can be
employed that suits the particular embedded system. Both the page-table size and
access time can be optimized.
Independent page sizes can be used for application modules, device drivers, system-
service routines, and data. Independent page-size selection enables system software
to more efficiently use memory by reducing fragmentation (unused memory). For
example, a large data structure can be allocated to a 16 MB page and a small I/O
device-driver can be allocated to a 1 KB page.
Page replacement can be tuned to minimize the occurrence of missing page-
translations. As described in the following section, the most-frequently used page
translations are stored in the translation look-aside buffer (TLB). Software is
responsible for deciding which translations are stored in the TLB and which
translations are replaced when a new translation is required. The replacement
strategy can be tuned to avoid thrashing, whereby page-translation entries are
constantly being moved in and out of the TLB. The replacement strategy can also be
tuned to prevent replacement of critical-page translations, a process sometimes
referred to as page locking.
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Chapter 6: Virtual-Memory Management
Description
Used to uniquely identify a software process during address
translation.
Virtex-II Pro™ Platform FPGA Documentation
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PID
March 2002 Release
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