Xilinx Virtex-II Pro PPC405 User Manual page 30

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Programmable Interval Timer
The programmable interval timer (PIT) is a 32-bit register that is decremented at the time-base
increment frequency. The PIT register is loaded with a delay value. When the PIT count
reaches 0, a PIT interrupt occurs. Optionally, the PIT can be programmed to automatically
reload the last delay value and begin decrementing again.
Fixed Interval Timer
The fixed interval timer (FIT) causes an interrupt when a selected bit in the time-base register
changes from 0 to 1. Programmers can select one of four predefined bits in the time-base
for triggering a FIT interrupt.
Watchdog Timer
The watchdog timer causes a hardware reset when a selected bit in the time-base register
changes from 0 to 1. Programmers can select one of four predefined bits in the time-base
for triggering a reset, and the type of reset can be defined by the programmer.
Debug
The PPC405 debug resources include special debug modes that support the various types
of debugging used during hardware and software development. These are:
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Debug events are
modes and debug events are controlled using debug registers in the processor. The debug
registers are accessed either through software running on the processor or through the
JTAG port. The JTAG port can also be used for board tests.
The debug modes, events, controls, and interfaces provide a powerful combination of
debug resources for hardware and software development tools.
describes these resources in detail.
PPC405 Interfaces
The PPC405 provides a set of interfaces that supports the attachment of cores and user
logic. The software resources used to manage the PPC405 interfaces are described in the
Core-Configuration Register, page 459
and electrical characteristics of these interfaces, refer to the
Manual. The following interfaces are provided:
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Processor Local Bus
The processor local bus (PLB) interface provides a 32-bit address and three 64-bit data buses
attached to the instruction-cache and data-cache units. Two of the 64-bit buses are attached
to the data-cache unit, one supporting read operations and the other supporting write
operations. The third 64-bit bus is attached to the instruction-cache unit to support
instruction fetching.
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Note: The time-base register alone does not cause interrupts to occur.
Internal-debug mode for use by ROM monitors and software debuggers
External-debug mode for use by JTAG debuggers
Debug-wait mode, which allows the servicing of interrupts while the processor appears
to be stopped
Real-time trace mode, which supports event triggering for real-time tracing
supported that allow developers to manage the debug process. Debug
Processor local bus interface
Device control register interface
Clock and power management interface
JTAG port interface
On-chip interrupt controller interface
On-chip memory controller interface
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Chapter 1: Introduction to the PPC405
Chapter 9,
. For information on the hardware operation, use,
PPC405 Processor Block
Virtex-II Pro™ Platform FPGA Documentation
Debugging,
March 2002 Release