Xilinx Virtex-II Pro PPC405 User Manual page 393

Alphabetical Instruction Listing
nmachhw
Negative Multiply Accumulate High Halfword to Word Modulo Signed
nmachhw rD, rA, rB
nmachhw. rD, rA, rB
nmachhwo rD, rA, rB
nmachhwo. rD, rA, rB
XO Instruction Form
4
0 6
Description
The high-order halfword of rA is multiplied by the high-order halfword of rB. The negated
signed product is added to the contents of rD and the sum is stored as a 33-bit temporary
result. The contents of rD are replaced by the low-order 32 bits of the temporary result. An
example of this operation is shown in
Pseudocode
Registers Altered
•
•
•
Exceptions
•
Compatibility
This instruction is implementation specific and is not guaranteed to be supported by other
PowerPC processors.
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
(OE=0, Rc=0)
(OE=0, Rc=1)
(OE=1, Rc=0)
(OE=1, Rc=1)
rD rA
1
1
←
× (
rB )
prod (rA)
0:31 0:15
−
←
1 × prod
nprod
0:31 0:31
←
temp nprod + (rD)
0:32 0:31
←
(rD) temp
1:32
rD.
CR[CR0] if Rc=1.
LT, GT, EQ, SO
XER[SO, OV] if OE=1
None.
www.xilinx.com
1-800-255-7778
rB OE
1 2 2
6 1 2
Figure 3-32, page
signed
0:15
signed
46
417.
R
Rc
3
1
701