Xilinx Virtex-II Pro PPC405 User Manual page 303

Alphabetical Instruction Listing
dcbst
Data Cache Block Store
dcbst rA, rB
X Instruction Form
31 0
0 6
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
•
•
•
If EA is cached by the data cache, the corresponding data cacheline is checked to see if it is
marked modified. If it is modified, it is stored to main memory and marked as unmodified.
The store operation is performed whether or not the corresponding storage attribute
indicates EA is cachable. No operation occurs if the data cacheline is unmodified, or if EA
is not cached.
Pseudocode
Registers Altered
•
Exceptions
•
•
This instruction is considered a "load" with respect to the above data-access exceptions. It
is considered a "store" with respect to data address-compare (DAC) debug exceptions.
Debug exceptions can occur as a result of executing this instruction.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
0 0 0 0 rA
1
1
The contents of register rB are used as the index.
If the rA field is 0, the base address is 0.
If the rA field is not 0, the contents of register rA are used as the base address.
←
rA |0) + ( rB )
EA (
Store modified data cacheline corresponding to EA
None.
Data storage—if the access is prevented by no-access-allowed zone protection. This
only applies to accesses in user mode when data relocation is enabled.
Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
Reserved bits containing a non-zero value.
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rB
1 2
6 1
R
54 0
3
1
611