Code Optimization Guidelines; Conditional Branches - Xilinx Virtex-II Pro PPC405 User Manual

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Code Optimization Guidelines

The following guidelines can help reduce program execution time in the PPC405.
Additional information on PowerPC code optimization can be found in The PowerPC
Compiler Writer's Guide.

Conditional Branches

Multi-way branches and compound branches can be implemented in several ways. The
implementation choice depends on problem specifics, including the number and
distribution of test conditions and the instruction timings and latencies. Usually, the
implementation involves a combination of conditional branches and unconditional
branches.
Conditional branches require the evaluation of conditional expressions. In evaluating
these expressions, performance can be improved by using instructions that update the CR
to reflect their results. These results are represented in the CR as boolean variables that can
be operated on using the CR-logical instructions. This usually yields better performance
than using other instructions to evaluate conditional expressions solely in the GPRs.
The following pseudocode provides a simple example of how the CR register and CR-
logical instructions can be used to improve the performance of conditional expressions by
eliminating branches. In this example, Var28–Var31 are boolean variables maintained as
bits in the CR[CR7] field (CR
binary value 0b1 and a false condition by using the binary value 0b0.
The above pseudocode can be implemented in assembler using branches as follows:
842
rlwinm r4, r4, 32−sh, sh, 31
rlwimi r4, r3, 32−sh, 0, sh−1
rlwinm r3, r3, 32−sh, sh, 31
rlwimi r3, r2, 32−sh, 0, sh−1
srawi r2, r2, sh
Shift-right algebraic, n = 2 (shift amount < 64)
subfic r31, r6, 32
srw r3, r3, r6
slw r0, r2, r31
or r3, r3, r0
addic. r31, r6, −32
sraw r0, r2, r31
ble $+8
r3, r0, 0
ori
sraw r2, r2, r6
Shift-right algebraic, n = 3 (shift amount < 32)
subfic r31, r6, 32
srw r4, r4, r6
slw r0, r3, r31
or r4, r4, r0
srw r3, r3, r6
slw r0, r2, r31
or r3, r3, r0
sraw r2, r2, r6
28:31
if (Var28 || Var29 || Var30 || Var 31) branch to target
bt 28, target
bt 29, target
bt 30, target
bt 31, target
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Appendix D: Programming Considerations
). These variables represent a true condition by using the
Virtex-II Pro™ Platform FPGA Documentation
March 2002 Release