Xilinx Virtex-II Pro PPC405 User Manual page 11

Terms
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Book-E An version of the PowerPC architecture designed specifically
for embedded applications.
Synonym for cacheline.
cache block
cacheline A portion of a cache array that contains a copy of contiguous
system-memory addresses. Cachelines are 32-bytes long and
aligned on a 32-byte address.
clear To write a bit value of 0.
Synonym for congruence class.
cache set
congruence class A collection of cachelines with the same index.
dirty An indication that cache information is more recent than the
copy in memory.
doubleword Eight bytes, or 64 bits.
effective address The untranslated memory address as seen by a program.
exception An abnormal event or condition that requires the processor's
attention. They can be caused by instruction execution or an
external device. The processor records the occurrence of an
exception and they often cause an interrupt to occur.
A buffer that receives and sends data and instructions between
fill buffer
the processor and PLB. It is used when cache misses occur and
when access to non-cacheable memory occurs.
flush A cache or TLB operation that involves writing back a modified
entry to memory, followed by an invalidation of the entry.
GB Gigabyte, or one-billion bytes.
halfword Two bytes, or 16 bits.
For cache arrays and TLB arrays, an indication that requested
hit
information exists in the accessed array.
interrupt The process of stopping the currently executing program so that
an exception can be handled.
invalidate A cache or TLB operation that causes an entry to be marked as
invalid. An invalid entry can be subsequently replaced.
KB Kilobyte, or one-thousand bytes.
line buffer A buffer located in the cache array that can temporarily hold the
contents of an entire cacheline. It is loaded with the contents of
a cacheline when a cache hit occurs.
little endian A memory byte ordering where the address of an item
corresponds to the least-significant byte.
logical address Synonym for effective address.
MB Megabyte, or one-million bytes.
memory Collectively, cache memory and system memory.
miss For cache arrays and TLB arrays, an indication that requested
information does not exist in the accessed array.
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