Xilinx Virtex-II Pro PPC405 User Manual page 401

Alphabetical Instruction Listing
oris
OR Immediate Shifted
oris rA, rS , UIMM
D Instruction Form
25
0 6
Description
The UIMM field is extended to 32 bits by concatenating 16 0-bits on the right. The contents
of the register rS are ORed with the extended UIMM field and the result is loaded into
register rA.
Pseudocode
Registers Altered
•
Exceptions
•
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
rS rA
1
1
← ∨
( rA ) (rS) (UIMM
rA.
None.
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1
6
||
16 0)
UIMM
R
3
1
709