List Insertion; Multiple-Precision Shifts - Xilinx Virtex-II Pro PPC405 User Manual

R
The unlock procedure writes a zero to the lock location. If access to the shared resource
includes write operations, most applications require a sync instruction to make the shared
resource modifications visible to all processors before releasing the lock.

List Insertion

The following example shows how the lwarx and stwcx. instructions are used to
implement simple LIFO (last-in-first-out) insertion into a singly linked list. If multiple
values must be changed atomically or the correct order of insertion depends on the
element contents, insertion cannot be implemented as shown below and instead requires a
more complicated strategy (such as lock synchronization).
In this example, list elements are data structures that contain pointers to the next element
in the list. A new element is inserted after an existing (parent) element. The next element
pointer in the parent element is copied (stored) unconditionally into the new element. A
pointer to the new element is stored conditionally into the parent element.
In this example, it is assumed that the parent element address is in r3, the new element
address is in r4, and the next element pointers are at offset zero in the respective element
data structure. It is also assumed that the next element pointer of each list element is in a
reservation granule separate from that of the next element pointer of all other list elements.
In the preceding example, livelock can occur in a multiprocessor system if two list
elements have next element pointers within the same reservation granule. If it is not
possible to allocate list elements such that next element pointers are in different reservation
granules, livelock can be avoided by using the following sequence:

Multiple-Precision Shifts

Following are programming examples for multiple-precision shifts. A multiple-precision
shift is a shift of an n-word quantity, where n > 1. The quantity to be shifted is contained in
n registers. The shift amount is specified either by an immediate value in the instruction or
by bits 27:31 of a register.
The following examples distinguish between the cases n = 2 and n > 2. If n > 2, the examples
yield the desired result only when the shift amount is restricted to the range 0–31. When
n > 2, the number of instructions required is 2n
840
lock: li r4,1
loop: bl test_and_set #test and set
bne- loop
isync
blr
unlock:sync
li r1,0
stw r1,0(r3) #store zero to lock location
blr
loop: lwarx r2,0,r3 #get next pointer
stw r2,0(r4) #store in new element
sync
stwcx. r4,0,r3 #add new element to list
bne- loop
lwz r2,0(r3) #get next pointer
loopl: mr r5,r2
stw r2,0(r4) #store in new element
sync
loop2: lwarx r2,0,r3 #get next pointer again
cmpw r2,r5
bne- loopl
stwcx. r4,0,r3 #add new element to list
bne- loop2
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Appendix D: Programming Considerations
#obtain new lock
#retry until old lock = 0
#synchronize context
#return
#delay until prior stores finish
#return
#synchronize memory (can omit if not MP)
#loop if reservation lost
#keep a copy
#synchronize memory
#loop if changed
#(updated by another processor)
#loop if reservation lost
−
1 (immediate shifts) or 3n
Virtex-II Pro™ Platform FPGA Documentation
−
1 (non-
March 2002 Release