Xilinx Virtex-II Pro PPC405 User Manual page 345

Alphabetical Instruction Listing
lswi
Load String Word Immediate
lswi rD, rA, NB
X Instruction Form
31
0 6
Description
An effective address (EA) is determined by the rA field as follows:
•
•
Let n specify the byte count. If the NB field is 0, n is 32. Otherwise, n is equal to NB.
Let nr specify the number of registers to load with data. nr = CEIL(n
Let R
the memory address referenced by EA are loaded into GPRs rD through R
sequence of registers wraps around to r0 if necessary. R
Bytes are loaded in each register starting with the most-significant register byte and ending
with the least-significant register byte. If the byte count is exhausted before R
the remaining bytes in R
Pseudocode
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
rD rA
1
1
If the rA field is 0, the EA is 0.
If the rA field is not 0, the contents of register rA are used as the EA.
specify the last register to be loaded with data. n consecutive bytes starting at
FINAL
FINAL
←
rA |0)
EA (
= 0
if NB
←
then n 32
←
else n NB
←
R (( rD + CEIL(n/4)
FINAL
−
← rD
reg 1
←
bit 0
do while n > 0
= 0
if bit
then
←
reg reg + 1
= 32
if reg
←
then reg 0
≠ rA ∨
if ((reg ) (reg
then (GPR(reg))
≠ rA ∨ = R
if ((reg ) (reg
FINAL
then (GPR(reg)
bit:bit+7
←
bit bit + 8
= 32
if bit
←
then bit 0
←
EA EA + 1
−
←
n n 1
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NB
1 2
6 1
are loaded with 0.
−
1) % 32)
= R
))
FINAL
←
0
))
←
) MS(EA,1)
597
÷
4).
. The
FINAL
= rD + nr − 1 (modulo 32).
FINAL
FINAL
R
0
3
1
is filled,
653