Branch And Flow-Control Instructions; Conditional Branch Control - Xilinx Virtex-II Pro PPC405 User Manual

Branch and Flow-Control Instructions

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Other exceptions can occur during user-mode program execution that are not directly
caused by instruction execution. These are also described in
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Branch and Flow-Control Instructions
Branch instructions redirect program flow by altering the next-instruction address non-
sequentially. Branches unconditionally or conditionally alter program flow forward or
backward using either an absolute address or an address relative to the branch-instruction
address. Branches calculate the target address using the contents of the CTR, LR, or fields
within the branch instruction. Optionally, a branch-return address can be automatically
loaded into the LR by setting the LK instruction-opcode bit to 1. This option is useful for
specifying the return address for subroutine calls and causes the address of the instruction
following the branch to be loaded in the LR. Branches are used for all non-sequential
program flow including jumps, loops, calls and returns.
Branch-conditional instructions redirect program flow if a tested condition is true. These
instructions can test a bit value within the CR, the value of the CTR, or both. Condition-
register logical instructions are provided to set up the tests for branch-conditional
instructions.

Conditional Branch Control

With branch-conditional instructions, the BO opcode field specifies the branch-control
conditions and how the branch affects the CTR. The BO field can specify a test of the CR
and it can specify that the CTR be decremented and tested. The BO field can also be
initialized to reverse the default prediction performed by the processor. The bits within the
BO field are defined as shown in
Table 3-4: BO Field Bit Definitions
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
If data translation is enabled, an attempt to access data in memory when a valid TLB
entry is not present causes the data TLB-miss interrupt handler to be invoked.
Instruction TLB-Miss Exception.
If instruction translation is enabled, an attempt to access instructions in memory when
a valid TLB entry is not present causes the instruction TLB-miss interrupt handler to be
invoked.
Machine-check exceptions.
Exceptions caused by external devices.
Exceptions caused by a timer.
Debug exceptions.
BO Bit
BO[0] CR Test Control
0—Test the CR bit specified by the BI opcode field for the value indicated by BO[1].
1—Do not test the CR.
BO[1] CR Test Value
0—Test for CR[BI]=0.
1—Test for CR[BI]=1.
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Table 3-4.
Description
Chapter 7:
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