Mitsubishi Electric Melsec iQ-R Series User Manual page 131

CH1 HART device variable status
Each HART device variable status sent from the connected HART-enabled device is stored. Eight bits are used for one HART
device variable, and two words of the buffer memory addresses are stored for each channel.
b15 b14 b13 b12 b11 b10 b9
Un\G2082
(2)
b15 b14 b13 b12 b11 b10 b9
Un\G2083
(4)
(1) PV value status
(2) SV value status
(3) TV value status
(4) QV value status
Each status has the following structure.
b15 b14 b13 b12 b11 b10 b9
b7 b6 b5 b4 b3 b2 b1
(4) (3) (2) (1)
(1) Device family specific status
(2) More device variable status available
(3) Limit status
(4) Process data status
HART device variable Description
status
Device family specific status The stored value is dependent on the device family of the HART-enabled device.
More device variable status Availability of additional device family specific status is stored. This bit indicates
available whether specific status of the device family is available for a device family
command.
• 1b: Other HART device variable status is available.
• 0b: Other HART device variable status is unavailable.
Limit status Indicates whether the value of the HART device variables is limited.
• 11b: Constant
• 01b: Lower limit
• 10b: Upper limit
• 00b: No limitation
Process data status The overall status of HART device variables or dynamic variables is saved.
• 11b: Good
• 01b: Poor accuracy
• 10b: Manual/Fixed
• 00b: Bad
■Refreshing cycle
The stored status information is automatically refreshed every HART cycle time.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device variable status primary
value (PV), secondary value (SV)
CH HART device variable status tertiary value
(TV), quaternary value (QV)
b8 b7 b6 b5 b4
b8 b7 b6 b5 b4
b8
b0
CH1 CH2
2082 2094
2083 2095
b3 b2 b1 b0
(1)
b3 b2 b1 b0
(3)
CH3 CH4 CH5
2106 2118 2130
2107 2119 2131
Supplemental information
For details on the stored value, refer to the
manual of the used HART-enabled device
or the specifications of the HART.
This bit indicates whether specific status of
the device family is available for a device
family command.
The combination of these four bits in each
status indicates the status of the HART
device variables.
■Example
When process data status is Manual/Fixed
(10b) and limit status is No limitation (00b),
the HART device variables are manually
controlled.
CH6 CH7 CH8
2142 2154 2166
2143 2155 2167
APPX
Appendix 3 Buffer Memory Areas
A
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