Mitsubishi Electric Melsec iQ-R Series User Manual page 112

Condition target setting [n]
Set an interrupt factor to be detected.
Setting value
0
1
2
3
4
5
• If a value other than the above is set, a condition target setting range error (error code: 181H) occurs.
• When an input signal (X) or a buffer memory area set in 'Condition target setting [n]' (Un\G232 to Un\G247) turns on, an
interrupt request is sent to the CPU module. However, when A/D conversion completed (5) is set, turning on 'A/D
conversion completed flag' (Un\G42) sends an interrupt request to the CPU module.
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Condition target setting [n]
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is Disable (0) for all areas.
Condition target channel setting [n]
Set a channel where an interrupt is detected.
Setting value
0
1
2
3
4
5
6
7
8
When an interrupt factor with channel specification is set in 'Condition target setting [n]' (Un\G232 to Un\G247), an interrupt
factor is monitored in the channel set by this area. When an interrupt factor of the input signal (X) is set, the setting in this area
is ignored.
If a value other than the above is set, a condition target channel setting range error (error code: 182H) occurs.
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Condition target channel
setting [n]
APPX
110
Appendix 3 Buffer Memory Areas
Setting details
Disable
Error flag (XF)
Warning output flag (Process alarm)
Warning output flag (Rate alarm)
Input signal error detection flag
A/D conversion completed
1 2 3 4
232 233 234 235
1 2 3 4 5
264 265 266 267 268
5 6 7 8 9
236 237 238 239 240
Setting details
All channels
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
6 7 8 9
269 270 271 272
10 11 12 13 14
241 242 243 244 245
10 11 12 13 14
273 274 275 276 277
15 16
246 247
15 16
278 279