Details Of Output Signals - Mitsubishi Electric Melsec iQ-R Series User Manual

Details of output signals

The following describes the details of the output signals for the A/D converter module which are assigned to the CPU module.
The I/O numbers (X/Y) described in this section are for the case when the start I/O number of the A/D converter module is set
to 0.
This section describes buffer memory addresses for CH1. For details on the buffer memory addresses for
CH2 and later, refer to the following.
Page 95 List of buffer memory addresses
HART cycle time maximum value/minimum value reset request
'HART maximum cycle time' (Un\G2078) and 'HART minimum cycle time' (Un\G2079) are reset to the HART current cycle
time by turning on and off 'HART cycle time maximum value/minimum value reset request' (Y2).
For the timing of turning on and off the signal, refer to the following.
Page 86 HART cycle time maximum value/minimum value reset completed flag
■Device number
The following shows the device number of this output signal.
Signal name
HART cycle time maximum value/minimum value reset request
HART device variables access request
Data inconsistency that may occur when data are read from some buffer memory areas can be prevented by turning off and
on 'HART device variables access request' (Y3).
For the applicable buffer memory areas and the timing of turning on and off the signal, refer to the following.
Page 87 HART device variables access flag
■Device number
The following shows the device number of this output signal.
Signal name
HART device variables access request
CH1 CH2 CH3 CH4
Y2
CH1 CH2 CH3 CH4
Y3
CH5 CH6 CH7 CH8
CH5 CH6 CH7 CH8
APPX
Appendix 2 I/O Signals
A
93