Mitsubishi Electric Melsec iQ-R Series User Manual page 107

Latest address of alarm history
Among Alarm history  (Un\G3760 to Un\G3919), a buffer memory address which stores the latest alarm code is stored.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Latest address of alarm history
Interrupt factor detection flag [n]
The detection status of the interrupt factor is stored.
Monitored value
0
1
When an interrupt factor occurs, an interrupt request is sent to the CPU module at the same time as when 'Interrupt factor
detection flag [n]' (Un\G4 to Un\G19) is turned to Interrupt factor (1).
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name 1
Interrupt factor detection flag [n] 4
Warning output flag (Process alarm upper limit)
The upper limit warning of the process alarm can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Normal, 1: Alarm ON
(2) b8 to b15 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Warning output flag (Process alarm upper limit)
■Warning output flag status
• When a value is out of the range specified in 'CH1 Process alarm upper upper limit value' (Un\G514), Alarm ON (1) is
stored in the corresponding bit of 'Warning output flag (Process alarm upper limit)' (Un\G36).
• When a warning is detected in any channel where the A/D conversion and the warning output setting (process alarm) are
enabled, 'Warning output signal' (X8) also turns on.
■Clearing Warning output flag
• When the digital operation value falls within the set range, the flag is automatically cleared.
• When 'Operating condition setting request' (Y9) is turned on and off, the flag is cleared.
CH1
3
2 3 4 5 6
5 6 7 8 9
b8 b7 b6 b5 b4 b3 b2
0 CH8 CH7 CH6 CH5 CH4 CH3 CH2
(1)
CH1
36
CH2 CH3 CH4
Description
No interrupt factor
Interrupt factor
7 8 9 10
10 11 12 13
b1 b0
CH1
CH2 CH3 CH4
CH5 CH6 CH7 CH8
11 12 13 14 15
14 15 16 17 18
CH5 CH6 CH7 CH8
APPX
Appendix 3 Buffer Memory Areas
16
19
A
105