Mitsubishi Electric Melsec iQ-R Series User Manual page 129

CH1 HART field device status
The status information sent from the connected HART-enabled device is stored.
b15 b14 b13 b12 b11 b10 b9
(2)
(3)
(1) HART field device status
(2) HART field device error information or answer code
(3) Communication error
The value stored in each bit is as follows.
■HART field device status (bit 0 to bit 7)
The status information of the connected HART-enabled device is stored. When each bit is turned on, the status of the HART-
enabled device is indicated as follows:
Target bit Status
bit0 Primary variable out of limits
bit1 Non-primary variable out of
limits
bit2 Loop current saturated
bit3 Loop current fixed
bit4 More status available/
unavailable
bit5 Cold start
bit6 Configuration changed
bit7 Device malfunction
■HART field device error code or answer code (bit 8 to bit 14)
The error information or answer code of the connected HART-enabled device is stored. The stored information differs
depending on the status of bit 15.
• When bit 15 is turned on, error information is stored. When each bit is turned on, the status of the HART-enabled device is
indicated as follows:
Target bit Error Information
bit8 Not used
bit9 Buffer overflow
bit10 Communication failure
bit11 Longitudinal parity error
bit12 Framing error
bit13 Overrun error
bit14 Vertical parity error
• When bit 15 is turned off, the answer code is stored. For details on the stored answer code, refer to the manual of the used
HART-enabled device.
■Refreshing cycle
The stored status information is refreshed every HART cycle time.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART field device status
b8 b7 b6 b5 b4 b3 b2
(1)
Description
The PV value is out of the operation limit range.
The SV, TV, or QV value is out of the operation limit range.
Current has reached the upper or lower limit and cannot increase or decrease.
This bit is turned on when the current value is fixed.
This bit indicates that the added status includes diagnostic information.
The HART-enabled device has been powered off or reset. This bit is turned on only when the HART-enabled
device is powered off or reset for the first time.
The settings of the HART-enabled device have been changed. When the HART-enabled device is write-
protected, this bit is not reset.
Because a serious error or failure has been detected in a HART-enabled device, the HART-enabled device
is not properly operated.
Description

A message to the HART-enabled device is too long for the receive buffer.
The communication has failed.
The longitudinal parity calculated by the device is not matched with the message check byte.
A stop bit of 1 byte or larger is not detected.
The data of 1 byte or larger in the receive buffer is overwritten before read.
The parity of one or multiple bytes received is not odd.
CH1 CH2
2080 2092
b1 b0
CH3 CH4 CH5
2104 2116 2128
CH6 CH7 CH8
2140 2152 2164
APPX
Appendix 3 Buffer Memory Areas
A
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