Mitsubishi Electric Melsec iQ-R Series User Manual page 121

CH1 Rate alarm upper limit value
For rate alarm, the digital output value is checked at every warning detection cycle and the change rate is calculated from the
check result. Use this area to set an upper limit value of the change rate of digital output values for each channel.
For details on the warning output function (rate alarm), refer to the following.
Page 35 Rate alarm
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Rate alarm upper limit value
■Setting range
The setting range is from -32768 to 32767 (-3276.8 to 3276.7%). (Set it in increments of 0.1%.)
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is 0 for all channels.
CH1 Rate alarm lower limit value
For rate alarm, the digital output value is checked at every warning detection cycle and the change rate is calculated from the
check result. Use this area to set a lower limit value of the change rate of digital output values for each channel.
For details on the warning output function (rate alarm), refer to the following.
Page 35 Rate alarm
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Rate alarm lower limit value
■Setting range
The setting range is from -32768 to 32767 (-3276.8 to 3276.7%). (Set it in increments of 0.1%.)
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is 0 for all channels.
• When using rate alarms, configure the 2-step settings of the rate alarm upper limit value and lower limit
value.
• In the channel where a set value satisfies the condition the "rate alarm lower limit value  the rate alarm
upper limit value", a rate alarm upper/lower limit setting value inversion error (error code: 1BAH) occurs.
• Since the default value is 0, change the value.
CH1 CH2 CH3 CH4
524 724 924 1124
CH1 CH2 CH3 CH4
526 726 926 1126
CH5 CH6 CH7 CH8
1324 1524 1724 1924
CH5 CH6 CH7 CH8
1326 1526 1726 1926
APPX
Appendix 3 Buffer Memory Areas
A
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