Mitsubishi Electric Melsec iQ-R Series User Manual page 128

HART maximum cycle time
The maximum HART cycle time is stored in increments of 10ms. The stored value is updated as the HART cycle time elapses.
Ex.
When the stored value is 100, the maximum HART cycle time is 1s (10010ms).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART maximum cycle time
■Resetting the stored value
The stored value of this area is reset to the value of 'HART current cycle time' (Un\G2077) in any of the following conditions.
• The first HART cycle time has elapsed after the CPU module is reset.
• 'HART cycle time maximum value/minimum value reset request' (Y2) is turned on and off.
HART minimum cycle time
The minimum HART cycle time is stored in increments of 10ms. The stored value is updated as the HART cycle time elapses.
Ex.
When the stored value is 100, the minimum HART cycle time is 1s (100 10ms).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART minimum cycle time
■Resetting the stored value
The stored value of this area is reset to the value of 'HART current cycle time' (Un\G2077) in any of the following conditions.
• The first HART cycle time has elapsed after the CPU module is reset.
• 'HART cycle time maximum value/minimum value reset request' (Y2) is turned on and off.
APPX
126
Appendix 3 Buffer Memory Areas
CH1 CH2 CH3
2078
CH1 CH2 CH3
2079
CH4 CH5 CH6
CH4 CH5 CH6
CH7 CH8
CH7 CH8