Mitsubishi Electric Melsec iQ-R Series User Manual page 113

Hart-enabled analog-digital converter module
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■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is All channels (0) for all areas.
CH1 Digital output value
The A/D-converted digital output value is stored as a 16-bit signed binary value.
b15 b14 b13 b12 b11 b10 b9
(2)
(1) Data section
(2) Sign bit 0: Positive, 1: Negative
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Digital output value
■Refreshing cycle
When time average or count average is performed, values are updated at every averaging process cycle. When the
processing other than them is performed, values are updated at every sampling cycle.
CH1 Digital operation value
A digital operation value obtained by the scaling function is stored as a 16-bit signed binary value.
b15 b14 b13 b12 b11 b10 b9
(2)
(1) Data section
(2) Sign bit 0: Positive, 1: Negative
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Digital operation value
■Refreshing cycle
When time average or count average is performed, values are updated at every averaging process cycle. When the
processing other than them is performed, values are updated at every sampling cycle.
When the scaling function is not used, the same value as 'CH1 digital output value' (Un\G400) is stored.
CH1 Maximum value, CH1 Minimum value
The maximum value and minimum value of digital operation values or digital output values are stored as 16-bit signed binary
values.
In the following cases, 'CH1 Maximum value' (Un\G404) and 'CH1 Minimum value' (Un\G406) are updated with the current
values.
• When 'Operating condition setting request' (Y9) is turned on and off and the setting is changed
• When 'Maximum value/minimum value reset request' (YD) is turned on and off
b8
b7
b6
b5
b4
b3
b2
(1)
CH1
400
b8
b7
b6
b5
b4
b3
b2
(1)
CH1
402
b1
b0
CH2
CH3
CH4
600
800
1000
b1
b0
CH2
CH3
CH4
602
802
1002
CH5
CH6
CH7
CH8
1200
1400
1600
1800
CH5
CH6
CH7
CH8
1202
1402
1602
1802
APPX
Appendix 3 Buffer Memory Areas
A
111

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