Xilinx Kintex-7 FPGA KC724 User Manual page 25

Each GTX Quad and its associated reference clocks (CLK0 and CLK1) are brought out to a
connector pad which interfaces with Samtec BullsEye connectors used with the Samtec
HDR-155805-01-BEYE cable assembly. Contact Samtec, Inc. for information about this or
other cable assemblies.
connector pinout.
X-Ref Target - Figure 1-14
Information for each GTX transceiver pin is shown in
Table 1-12: GTX Transceiver Pins
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
Figure 1-14
A
GTX Connector Pad
Figure 1-14: A – GTX Connector Pad. B – GTX Connector Pinout
U1 FPGA Pin Net Name
Y2 115_TX0_P
Y1 115_TX0_N
AA4 115_RX0_P
AA3 115_RX0_N
V2 115_TX1_P
V1 115_TX1_N
Y6 115_RX1_P
Y5 115_RX1_N
U4 115_TX2_P
U3 115_TX2_N
W4 115_RX2_P
W3 115_RX2_N
T2 115_TX3_P
T1 115_TX3_N
www.xilinx.com
A shows the connector pad.
B
P
P
P
P
P
GTX Connector Pinout
Table 1-12.
Quad Connector
115
115
115
115
115
115
115
115
115
115
115
115
115
115
Detailed Description
Figure 1-14 B shows the
GTX
P
N
N
N P
N
P
N
N
P
N
N
P
N
N
UG930_c1_02_061412
Trace Length
(mils)
J83 2,805
J83 2,806
J83 2,898
J83 2,898
J83 2,525
J83 2,523
J83 2,489
J83 2,489
J83 2,549
J83 2,549
J83 2,308
J83 2,309
J83 2,840
J83 2,840
Send Feedback
25