User Push Buttons (Active High); User Test I/O - Xilinx SP623 User Manual

Chapter 1: SP623 Board Features and Operation
Table 1-9: User DIP Switches

User Push Buttons (Active High)

[Figure
SW5 and SW6 are active-High user push buttons that are connected to user I/O pins on the
FPGA, as identified in
by the user.
Table 1-10: User Push Buttons

User Test I/O

[Figure
A standard 2 x 6, 100-mil pitch header (J44) brings out 6 FPGA I/O for test purposes.
Table 1-11
Table 1-11: User Test I/O
20
FPGA Pin Net Name
J26 SW1
J25 SW2
K26 SW3
K24 SW4
G26 SW5
G25 SW6
H26 SW7
H24 SW8
1-2, callout 15]
Table 1-10. These switches can be used for any purpose determined
FPGA Pin Net Name
M26 PB_SW1
M24 PB_SW2
1-2, callout 16]
lists these pins.
FPGA Pin
U1 IO_L40N_M3DQ7_3_U1
U2 IO_L40P_M3DQ6_3_U2
V1 IO_L39N_M3LDQSN_3_V1
V3 IO_L39P_M3LDQS_3_V3
AA13 IO_L36N_2_AA13
AB13 IO_L36P_2_AB13
www.xilinx.com
Reference
Designator
SW7
Reference
Designator
SW6
SW4
Net Name J44 Pin
2
4
6
8
10
12
SP623 Board User Guide
UG751 (v1.0) May 22, 2010