Usb-To-Uart Bridge - Xilinx Kintex-7 FPGA KC724 User Manual

Chapter 1: KC724 Board Features and Operation
Table 1-13:

USB-to-UART Bridge

Callout 28,
Communications between the KC724 board and a host computer are through a USB cable
connected to J79. Control is provided by U34, a USB-to-UART bridge (Silicon Laboratories
CP2103).
Table 1-14: USB Mini-B Receptacle Pin Assignments and Signals
J79 Pin
The CP2103 supports an I/O voltage range of 1.8V to 3.3V on the KC724 board. Xilinx
UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins:
•
•
•
•
Connections of these signals between the FPGA and the CP2103 at U34 are listed in
Table
Table 1-15: FPGA to UART Connections
FPGA (U1)
Pin Function Direction
J18 RTS Output
H20 CTS
G20 TX Output
J17 RX
28
Send Feedback
GTX Transceiver Clock Inputs to the FPGA (Cont'd)
U1 FPGA Pin Net Name
J7 117_REFCLK1_N
C8 118_REFCLK0_P
C7 118_REFCLK0_N
E8 118_REFCLK1_P
E7 118_REFCLK1_N
Figure 1-2.
Table 1-14 lists the pin assignments and signals for the USB connector J79.
Signal Name
1 VBUS
2 USB_DATA_N
3 USB_DATA_P
4 GROUND
Transmit (TX)
Receive (RX)
Request to Send (RTS)
Clear to Send (CTS)
1-15.
IOSTANDARD
LVCMOS18
Input LVCMOS18
LVCMOS18
Input LVCMOS18
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Quad
117
118
118
118
118
Description
+5V into the CP2103 USB-to-UART bridge at U34.
Used to sense USB network connection.
Bidirectional differential serial data (N-side).
Bidirectional differential serial data (P-side).
Signal ground.
Schematic Net
Name
USB_CTS_I_B
USB_RTS_0_B
USB_RXD_I
USB_TXD_0
KC724 GTX Transceiver Characterization Board
Connector
J85
J86
J86
J86
J86
Device (U34)
Pin Function Direction
22 CTS Input
23 RTS Output
24 RXD Input
25 TXD Output
UG932 (v2.2) October 10, 2014