Xilinx Kintex-7 FPGA KC724 User Manual page 27

Table 1-12: GTX Transceiver Pins (Cont'd)
Information for each GTX transceiver clock input is shown in
Table 1-13:
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
U1 FPGA Pin Net Name
F6 117_RX3_P
F5 117_RX3_N
D2 118_TX0_P
D1 118_TX0_N
E4 118_RX0_P
E3 118_RX0_N
C4 118_TX1_P
C3 118_TX1_N
D6 118_RX1_P
D5 118_RX1_N
B2 118_TX2_P
B1 118_TX2_N
B6 118_RX2_P
B5 118_RX2_N
A4 118_TX3_P
A3 118_TX3_N
A8 118_RX3_P
A7 118_RX3_N
GTX Transceiver Clock Inputs to the FPGA
U1 FPGA Pin Net Name
R8 115_REFCLK0_P
R7 115_REFCLK0_N
U8 115_REFCLK1_P
U7 115_REFCLK1_N
L8 116_REFCLK0_P
L7 116_REFCLK0_N
N8 116_REFCLK1_P
N7 116_REFCLK1_N
G8 117_REFCLK0_P
G7 117_REFCLK0_N
J8 117_REFCLK1_P
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Detailed Description
Quad Connector
117 J85
117 J85
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
Table 1-13.
Quad Connector
115 J83
115 J83
115 J83
115 J83
116 J84
116 J84
116 J84
116 J84
117 J85
117 J85
117 J85
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Trace Length
(mils)
2,873
2,872
2,842
2,844
3,048
3,049
2,629
2,628
2,597
2,597
2,787
2,789
2,681
2,680
3,044
3,044
3,515
3,515
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