Xadc - Xilinx Kintex-7 FPGA KC724 User Manual

Chapter 1: KC724 Board Features and Operation
Table 1-18: VITA 57.1 FMC2 HPC Connections at JA2 (Cont'd)
Notes:
1. This signal is not directly connected to the FPGA. The value in the leftmost
Table 1-19
Table 1-19: Power Supply Voltages for the HPC Connector

XADC

Callout 31,
7 series FPGAs provide an analog front end (XADC) block. The XADC block includes a
dual 12-bit, 1 MSPS analog-to-digital convertor (ADC) and on-chip sensors. See 7 Series
FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480)
The KC724 board supports the internal FPGA sensor measurement capabilities of the
XADC. Internal measurements of the die temperature, VCCINT and VCCAUX can be
monitored using the ChipScope™ Pro tool. The KC724 board provides two ways of setting
the XADC reference voltage:
•
•
Note:
40
Send Feedback
U1 FPGA Pin
(1)
U23.6 FMC1_FMC2_TMS
column represents the device and pin the signal is connected to. For example,
U39.10 = U39 pin 10.
lists the power supply voltages for the HPC connectors.
Allowable Voltage Range Number
Voltage
Supply
FMC1
V VCCO_HP VCCO_HR
ADJ
3P3V 3.3V
AUX
3P3V 3.3V
12P0V 12V
Figure 1-2.
Jumper pins 1-2 (REG) on J142: In this configuration, an onboard,
low-temperature-coefficient 1.25V reference (U45, Texas Instruments part number
REF3012AIDBZT) is connected to XADC VREFP.
Jumper pins 2-3 (AGND) on J142: In this configuration, the FPGA's XADC uses an
internal reference circuit.
A jumper should be installed in one of the two positions during normal operation.
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Net Name
I
MAX
of Pins (Amps)
FMC2
4 4
1 0.020
4 3
2 1
[Ref 2] for details on the capabilities of the analog front end.
KC724 GTX Transceiver Characterization Board
FMC Pin
D33
Maximum
Tolerance
Capacitive Load
±5% 1,000 µF
±5% 150 µF
±5% 1,000 µF
±5% 1,000 µF
UG932 (v2.2) October 10, 2014