Xilinx Kintex-7 FPGA KC724 User Manual page 43

Default Jumper and Switch Positions
Table A-1
jumpers must be installed except where specifically noted in this user guide. PCB
Assembly Drawing 0431643 shows the location and the default placement of all jumpers
on their respective connectors on the board.
Note:
Table A-1: Default Jumper Settings
Reference
Designator
J48 <None>
J49 <None>
J50 <None>
J4 UTIL_3V3
J24 UTIL_5V0
J78 VTT SOURCE
J141 VCCADC SELECT
J142 VREF SEL
J140 PMBUS CTRL
DIP switch SW10 enables the supply of onboard core power to the FPGA. For normal
operation positions 1 through 6 must be set to the ON position as shown in
X-Ref Target - Figure A-1
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
lists the jumpers that must be installed on the board for proper operation. These
Any jumper not listed in
Name
Upper-left
Upper-left
Upper-left
Upper-left
Upper-left
Upper-left
Upper-middle
Upper-middle
Upper-right
Figure A-1: Default Switch Settings
www.xilinx.com
Table A-1 should be left open for normal operation.
Board
Jumper
Location
CTRL (1–2)
CTRL (1–2)
CTRL (1–2)
CTRL (1–2)
CTRL (1–2)
VTT → GND (1–2)
VCCAUX (1–2)
REG (1–2)
ALWAYS ON (2-3)
SW10
Pin 1 VCCINT
VCCAUX
VCCBRAM
VCCAUX_IO
VCCO_HP
VCCO_HR
NC
NC
UG932_aB_01_062812
Appendix A
Comments
UCD9248 reset pin
UCD9248 reset pin
UCD9248 reset pin
Red 20A jumper
Figure A-1.
43
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