User Push Buttons (Active High); Bert Headers - Xilinx Virtex-II Pro ML324 User Manual

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10. User Push Buttons (Active High)

There are four active-high push buttons, as shown in
on the FPGA. These push buttons can be used for any purpose that the user sees fit.
Table 12: User Push Buttons

11. BERT Headers

There is one pair of 72-position headers intended to be used for parallel Bit Error Rate
Testing (BERT). The odd numbered pins of the BERT headers J56 and J55 are connected to
user I/O pins (see
and J55 are connected to GND. The third row of header pins (J49) to the left of J55 are
connected to VCCO. This gives the user the ability to jumper I/O pins on J56 to GND and
I/O pins on J55 to either VCCO or GND.
Table 13: BERT Headers J56 and J55
Virtex-II Pro ML324 and ML325 Platform
UG063 (v1.2) May 30, 2006
Label
SW7 D30
SW6 E30
SW3 AL18
SW8 AK18
Table 13, which spans multiple pages). The even numbered pins of J56
ML324 ML325
Header
J56
Pin Pin
1 H34 D42
2 H33 D41
3 H38 E42
4 H37 E41
5 J39 F42
6 J38 F41
7 K33 G41
8 K34 G42
9 K39 J42
10 K38 J41
11 L37 K41
12 L36 K42
13 L39 L42
14 L38 L41
15 M34 N42
16 M33 N41
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Table
ML324 ML325
Pin Pin
G33
F33
D34
C34
ML324
Header
Polarity
J55
N 1 AB35
P 3 AB34
N 5 AB37
P 7 AB36
N 9 AC39
P 11 AC38
N 13 AD34
P 15 AD33
N 17 AD38
P 19 AD37
N 21 AE37
P 23 AE36
N 25 AE39
P 27 AE38
N 29 AF34
P 31 AF33
Detailed Description
12, connected to user I/O pins
ML325
Polarity
Pin Pin
AB37 N
AB36 P
AD38 N
AD37 P
AF40 N
AF39 P
AG37 N
AG38 P
AK40 N
AK39 P
AK36 N
AK35 P
AM39 N
AM38 P
AP39 N
AP38 P
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