System Architecture - Analog Devices ADSP-TS201S EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board.
JTAG
Header
100MHz SCLKin
Clock Mult
(Default 5x)
LEDs
PBs
20MHz
Osc
1.5V
2.5V
1.05V
Power Regulation
Figure 2-1. System Architecture
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-TS201S TigerSHARC processor. The processor is powered by
three separate regulators for the core, internal DRAM, and IO. The pro-
2-2
JTAG Port
PLL
FLAGs
IRQs
JTAG Port
PLL
3.3V IRQs
5V
FLAGs
1.05V VDD_CORE
1.5V VDD_DRAM
2.5V VDD_IO
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
CPLD I/O
Header
CPLD
External Bus
Interface Unit
ADSP-TS201
Link Port 0
Link Port 1
Link Port 2
Link Port 3
External Bus
Interface Unit
ADSP-TS201
Link Port 0
Link Port 1
Link Port 2
Link Port 3
Stereo Stereo
Jack Jack
AD1854 AD1871
DAC ADC
Flash
(512K x 8 bits)
SDRAM 32MB
(2chips x 4M x 32bits)
EBIU
Analog Devices
Type A
EZ-Kit Expansion
Interface
Link Port
Connectors
4 - RJ45
(2 per port)