System Architecture - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF561 Blackfin processor. The processor has IO voltage of 3.3V.
The core voltage and the core clock rate can be set on the fly by the pro-
cessor. The input clock is 30 MHz.
2-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual