System Architecture - Analog Devices ADSP-BF535 EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board.
JTAG Header
SRAM
20MHz
Oscillator
32.768KHz
Crystal
Power
Management
3.3V
5V A5V 3.3V
Power
Regulation
Figure 2-1. System Architecture
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF535 Blackfin processor. The processor has a default core voltage
of 1.5V. Refer to
tion about changing the core voltage without halting the processor. The
voltage of the processor's peripheral interface is 3.3V.
A 20 MHz oscillator supplies the input clock to the processor. The speed
at which the core and peripherals operate is determined by the configura-
tion of the multiplier select switch (
2-2
544KB Flash
(U4)
External Bus Interface
Unit
ADSP-BF535
processor
CLK_IN
(U1)
RTC
VDD_INT
SPORT0
VDD_EXT
AD1885
Codec
(U7)
"Power Management" on page 1-12
SW2
ADSP-BF535 EZ-KIT Lite Evaluation System Manual
4M X 32bit
SDRAM
(U5, U6)
SPI 1:0
UART1:0
Timer2:0
Expansion
Connectors
(P1, P2, P3)
SPORT1
USB
LEDs, PBs
PF15:0
and Clock
Logic
SPORT0
Connector
Stereo LINEIN/
MIC and
LINEOUT
Connectors
for more informa-
) at reset (see "Processor PLL Setup