External Port; Expansion Interface - Analog Devices ADSP-TS201S EZ-KIT Lite Manual

cessor core voltage is set to 1.05V. The internal DRAM is powered by an
external 1.5V regulator. Finally, the external interface (IO) operates at
2.5V but can accept up to 3.3V levels.
A 20 MHz SMT oscillator, in conjunction with a clock generator set to
5x, supply the input clock to the processors. The speed at which the core
operates is determined by pull-up and pull-down resistors on both the
clock generator (
more information, see
the processor core runs at 500 MHz (20 MHz x 5 (
=500 MHz).

External Port

The external port (EP) connects to a 512K x 8-bit flash memory. The
flash memory connects to the boot memory select (
bank 0 ( ) pins. The flash can be used to boot the processor as well as
~MS0
to store information during normal operation. Refer to
on page 1-9 for more information.
The EP also connects to a 4MB x 64-bit SDRAM. Refer to
Interface" on page 1-8

Expansion Interface

The expansion interface consists of three connectors. The following table
shows the interfaces each connector provides. For the exact pinout of the
connectors, refer to
Table 2-1. Expansion Interface Connectors
Connector
J1
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
ADSP-TS201S EZ-KIT Lite Hardware Reference
) and the
U1 SCLKRAT2–0
"Clock Mode Settings" on page
for more information.
"Expansion Interface" on page
Interfaces
5V, , address, data
GND
bit of each of the processors. For
2-12. By default,
) x 5 (
U1
) and memory
~BMS
"Flash Memory"
B-11.
)
SCLKRAT
"SDRAM
2-3