Siemens Simatic S7-200 System Manual page 308

Instruction Set
Understanding the Interrupt Priority and Queuing
Interrupts are prioritized according to the fixed priority scheme shown below:
Communication (highest priority)
I/O interrupts
Time-based interrupts (lowest priority)
Interrupts are serviced by the CPU on a first-come-first-served basis within their respective
priority assignments. Only one user-interrupt routine is ever being executed at any point in
time. Once the execution of an interrupt routine begins, the routine is executed to completion.
It cannot be pre-empted by another interrupt routine, even by a higher priority routine.
Interrupts that occur while another interrupt is being processed are queued for later
processing.
The three interrupt queues and the maximum number of interrupts they can store are shown
in Table 10-16.
Table 10-16
Queue
Communications queue
I/O Interrupt queue
Timed Interrupt queue
Potentially, more interrupts can occur than the queue can hold. Therefore, queue overflow
memory bits (identifying the type of interrupt events that have been lost) are maintained by
the system. The interrupt queue overflow bits are shown in Table 10-17. You should use
these bits only in an interrupt routine because they are reset when the queue is emptied, and
control is returned to the main program.
Table 10-17
Description (0 = no overflow, 1 = overflow)
Communication interrupt queue overflow
I/O interrupt queue overflow
Timed interrupt queue overflow
10-120
Interrupt Queues and Maximum Number of Entries per Queue
CPU 212
4
4
2
Special Memory Bit Definitions for Interrupt Queue Overflow Bits
CPU 214 CPU 215
4 4
16 16
4 8
SM Bit
SM4.0
SM4.1
SM4.2
S7-200 Programmable Controller System Manual
C79000-G7076-C230-02
CPU 216
8
16
8