Siemens Simatic S7-200 System Manual page 209

High-Speed Counter Definition, High-Speed Counter
L
A
EN
D
HSC
MODE
EN
N
S
HDEF HSC, MODE
T
L
HSC N
212 214
Understanding the High-Speed Counter Instructions
High-speed counters count high-speed events that cannot be controlled at CPU scan rates.
HSC0 is an up/down software counter that accepts a single clock input. The counting
direction (up or down) is controlled by your program, using the direction control bit. The
maximum counting frequency of HSC0 is 2 KHz.
HSC1 and HSC2 are versatile hardware counters that can be configured for one of
twelve different modes of operation. The counter modes are listed in Table 10-5. The
maximum counting frequency of HSC1 and HSC2 is dependent on your CPU. See
Appendix A.
Each counter has dedicated inputs for clocks, direction control, reset, and start where these
functions are supported. For the two-phase counters, both clocks may run at their maximum
rates. In quadrature modes, an option is provided to select one time (1x) or four times (4x)
the maximum counting rates. HSC1 and HSC2 are completely independent of each other
and do not affect other high-speed functions. Both counters run at maximum rates without
interfering with one another.
Figure 10-16 shows an example of the initialization of HSC1.
S7-200 Programmable Controller System Manual
C79000-G7076-C230-02
The High-Speed Counter Definition instruction assigns a
MODE to the referenced high-speed counter (HSC). See
HDEF
Table 10-5.
The High-Speed Counter instruction, when executed,
configures and controls the operational mode of the high-speed
counter, based on the state of the HSC special memory bits.
The parameter N specifies the high-speed counter number.
HSC
Only one HDEF box may be used per counter.
Operands:
215 216
HSC: 0 to 2
MODE: 0 (HSC0)
0 to 11 (HSC1 or 2)
N: 0 to 2
Instruction Set
10-21