Reset Source; Boot Option; Table 5. Boot Related Switch; Table 6. Boot Related Jumpers - ST STM32F779I-EVAL User Manual

Hardware layout and configuration
6.4

Reset source

The reset signal of the STM32F779I-EVAL evaluation board is active low and the reset
sources include:
•
Reset button B1
•
Debugging tools from JTAG/SWD connector CN16 and ETM trace connector CN12
•
Daughterboard from CN5
•
Embedded ST-LINK/V2-1
•
RS232 connector CN7 pin 8 for ISP.
Note: The jumper JP5 must be closed when the RESET is handled by the CN7 pin 8 of the
RS-232 connector (CTS signal).
6.5

Boot option

The STM32F779I-EVAL evaluation board can boot from:
•
Embedded user Flash memory
•
System memory with boot loader for ISP
•
Embedded SRAM for debugging
The boot option is configured by setting the switch SW1 (BOOT) and the boot base address
programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes. The BOOT can be
configured also via RS-232 connector CN7.
Switch
configuration
0<->1
0<->1
Jumper
JP1
Note: R124 must be removed when boot loader starts up.This prevents the USB_PHY continuous
clock from interfering with the USART Rx IOs and the SPI Clock IOs.
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Table 5. Boot related switch

Boot address
option bytes
BOOT_ADD0
[15:0]
SW1
BOOT_ADD1
SW1 [15:0]

Table 6. Boot related jumpers

The Bootloader_BOOT is managed by pin 6 of connector CN7 (RS232 DSR signal)
when JP1 is closed. This configuration is used for boot loader application only.
Default Setting: Not fitted
DocID029088 Rev 3
STM32F779I-EVAL boot from BOOT_ADD0[15:0]
ST programmed value: Flash on ITCM at 0x0020 0000.
(Default setting)
STM32F779I-EVAL boot from BOOT_ADD1[15:0]
ST programmed value: System boot loader at 0x0010 0000
Description
Boot space
UM2036