Hitachi HD6473867 Hardware Manual page 209

Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL Description
0 Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1 Setting conditions:
Set when the TCFL value matches the OCRFL value
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL Description
0 TCFL overflow interrupt request is disabled
1 TCFL overflow interrupt request is enabled
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL Description
0 TCFL clearing by compare match is disabled
1 TCFL clearing by compare match is enabled
201
(initial value)
(initial value)
(initial value)