Operation - Hitachi HD6473867 Hardware Manual

9.7.3

Operation

1. 16-bit event counter operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Figure 9-
19 shows an example of the software processing when ECH and ECL are used as a 16-bit event
counter.
Clear CH2 to 0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Figure 9-19 Example of Software Processing when Using ECH and ECL as 16-Bit Event
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset.
They can also be used as a 16-bit event counter by carrying out the software processing shown in
the example in figure 9-19. The operating clock source is asynchronous event input from the AEVL
pin. When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH
and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL
count values each return to H'00, and counting up is restarted. When overflow occurs, the IRREC
bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the
CPU.
2. 8-bit event counter operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
Figure 9-20 shows an example of the software processing when ECH and ECL are used as 8-bit
event counters.
Start
Clear OVH and OVL to 0
End
Counter
246