Hitachi HD6473867 Hardware Manual page 81

3. Interrupt enable register 2 (IENR2)
Bit 7
IENDT
Initial value 0
Read/Write R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT Description
0 Disables direct transfer interrupt requests
1 Enables direct transfer interrupt requests
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD Description
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG Description
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
6 5
IENAD — IENTG
0 0
R/W R/W
4 3
IENTFH IENTFL
0 0
R/W R/W R/W
70
2 1 0
IENTC IENEC
0 0 0
R/W R/W
(initial value)
(initial value)
(initial value)